1. Field of the Invention
The present invention relates to the field of data transfer. More particularly, the present invention relates to a circuit and method for replacing address translations contained in an address translation unit.
2. Description of Art Related to the Invention
For over a decade, a number of system architectures have been developed with input/output ("I/O") devices accessing main memory through direct virtual memory accesses (DVMAs) using virtual addresses, instead of direct memory accesses ("DMAs") using physical addresses. One advantage associated with DVMA systems has been the simplification of data accesses by the I/O device. For example, I/O devices accessing memory through DMAs ("DMA I/O devices") must be controlled to "scatter" (or allocate) data to a number of potentially discontiguous physical pages as well as to "gather" data. Gathering data that exceeds one page in length is normally accomplished by accessing a group of discontiguous physical pages. In contrast, I/O devices that access main memory through DVMAs ("DVMA I/O devices") do not require such control because data accesses are made through contiguous virtual pages.
Although the DVMA systems have simplified this "scatter-gather" problem, these systems require the virtual addresses issued by the DVMA I/O devices to be translated into physical addresses before data can be accessed from main memory. As shown in FIG. 1, a conventional DVMA system 100 utilizes an I/O Memory Management Unit "I/O MMU" 110, sometimes referred to as an I/O Translation Lookahead Buffer, to translate virtual addresses to physical addresses utilized by main memory 120. As shown, the I/O MMU 110 is implemented within a bridge element 130 that couples an I/O bus 140 and a system bus 150.
Typically, the I/O MMU 110 is often configured to contain a limited number "r" of address translations to increase system performance with minimal additional costs. Thus, a plurality of I/O DVMA devices 160.sub.1 -160.sub.i ("i" being a whole number, i.gtoreq.2) are restricted to collectively use at most "r" virtual pages without mitigating system performance. If a requested address translation is not contained within the I/O MMU 110, resulting in an I/O MMU "miss", the requested address translation must be fetched from main memory 120 which contains all potential address translations. Of course, such fetching reduces system performance.
With the emergence of multi-media communications, networks are now being required to support multiple data types. As a result, network manufacturers are tending to concentrate their efforts toward asynchronous transfer mode ("ATM") networks. In ATM networks, a large number of virtual channels, perhaps hundreds, can be in operation simultaneously. Hence, if the DVMA system 100 is configured to support an ATM network coupled to I/O network interface logic 170, it would experience significant performance degradation caused by excessive fetching of address translations from main memory.
To substantially avoid performance degradation, an address translation unit ("ATU") may be implemented within a Network Interface Circuit (or Cord) ("NIC"). The ATU would contain a set of virtual-to-physical address translations, thereby providing an ability to bypass the I/O MMU. These address translations are modifiable, and thus, would require a "flush" operation scheme to remove address translations that no longer reflect current or active translations. This is necessary to maintain coherency.
Although system software normally has the responsibility of issuing and controlling flush operations, it requires intensive system and code analysis to remove code related to superfluous flush operations or to add code to support requisite flush operations that were not previously coded. Such intensive system and code analysis is prevalent, especially during development and initial placement in the market when flaws in performance can have substantial adverse effects on the success of the product.
Hence, it would be advantageous to develop hardware circuitry to at least assist system software by checking for the existence of a particular virtual page in the ATU before loading a new address translation for that page. This circuitry would detect missed software flush operations, which would be especially useful during system software development.